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TC58DVM72A1FTI0 2003-03-19 1/34 tentative toshiba mos digital integrated circuit silicon gate cmos 128-mbit (16m u 8 bits) cmos nand e 2 prom description the device is a 128-mbit (138,412,032) bit nand elec trically erasable and prog rammable read-only memory (nand e 2 prom) organized as 528 bytes u 32 pages u 1024 blocks. the device uses single power supply (2.7 v to 3.6 v for v cc ). the device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. th e erase operation is impl emented in a single block unit (16 kbytes 512 bytes: 528 bytes u 32 pages). the device is a serial-type memory device which utilizes the i/o pins for both address and data input/output as well as for command inputs. the erase an d program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which requir e high-density non-volatile memory data storage. features x organization memory cell allay 528 u 32k u 8 register 528 u 8 page size 528 bytes block size (16k 512) bytes x modes read, reset, auto page program auto block erase, status read x mode control serial input/output command control x power supply vcc: 2.7v to 3.6v x program/erase cycles 1e5 cycle (with ecc) x access time cell array to register 25 p s max serial read cycle 50 ns min x operating current read (50 ns cycle) 10 ma typ. program (avg.) 10 ma typ. erase (avg.) 10 ma typ. standby 50 p a max. x package tsop i 48-p-1220-0.50 (weight:0.53g typ) x toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in ge neral can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibil ity of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to a void situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. x the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction o r failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy con trol instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this docume nt shall be made at the customer?s own risk. x the products described in this document are subject to the foreign exchange and foreign trade laws. x the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d b y toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from it s use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. x the information contained herein is subject to change without notice. 000707eba1
TC58DVM72A1FTI0 2003-03-19 2/34 pin assignment (top view) pinnames i/o1 to i/o8 i/o port ce chip enable we write enable re read enable cle command latch enable ale address latch enable wp write protect by / ry ready/busy gnd ground input v cc power supply v ss ground nc nc nc nc i/o8 i/o7 i/o6 i/o5 nc nc nc v cc v ss nc nc nc i/o4 i/o3 i/o2 i/o1 nc nc nc nc 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 nc nc nc nc nc gnd by / ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc nc nc
TC58DVM72A1FTI0 2003-03-19 3/34 block diagram absolute maximum ratings symbol rating value unit v cc power supply voltage 0.6~4.6 v v in input voltage for control pins 0.6~4.6 v v i/o input/output voltage for i/o pins 0.6 v~v ccq 0.3 v ( ? 4.6 v) p d power dissipation 0.3 w t solder soldering temperature(10s) 260 c t stg storage temperature 55~150 c t opr operating temperature -40~85 c capacitance *(ta =25c, f= 1 mhz) symb0l parameter condition min max unit c in input v in 0 v 10 pf c out output v out 0 v 10 pf * this parameter is periodically sampled and is not tested for every device. v cc i/o control circuit status register address register command register column buffer column decoder data register sense amp memory cell array control hv generator row address decoder logic control by / ry i/o1 v ss i/o8 to wp ce cle ale we re by / ry row address buffer decoder
TC58DVM72A1FTI0 2003-03-19 4/34 valid blocks (1) symbol parameter min typ. max unit n vb number of valid blocks 1004 1024 blocks (1) the device occasionally contains unusable blocks. refer to application note (13) toward the end of this document. (2) the first block (block address #00) is guaranteed to be a valid block at the time of shipment. recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 3.3 3.6 v v ih high level input voltage 2.0 v cc 0.3 v v il low level input voltage 0.3 * 0.8 v * 2 v (pulse width lower than 20 ns) dc characteristics (ta = -40 to 85c, v cc 2.7 v to 3.6 v) symbol parameter condition min typ. max unit i il input leakage current v in 0 v to v ccq r 10 p a i lo output leakage current v out 0 v to v ccq r 10 p a i cco1 operating current (serial read) ce v il , i out 0 ma, t cycle 50 ns 10 30 ma i cco3 operating current (command input) t cycle 50 ns 10 30 ma i cco4 operating current (data input) t cycle 50 ns 10 30 ma i cco5 operating current (address input) t cycle 50 ns 10 30 ma i cco7 programming current 10 30 ma i cco8 erasing current 10 30 ma i ccs1 standby current ce v ih, wp 0 v/v ccq 1 ma i ccs2 standby current ce v ccq 0.2 v, wp 0 v/v ccq 10 50 p a v oh high level output voltage i oh ma 2.4 v v ol low level output voltage i ol 2.1 ma 0.4 v i ol ( by / ry ) output current of by / ry pin v ol 0.4 v 8 ma
TC58DVM72A1FTI0 2003-03-19 5/34 ac characteristics and recommended operating conditions (ta -40 to 85c, v cc 2.7 v to 3.6 v) symbol parameter min max unit notes t cls cle setup time 0 ns t clh cle hold time 10 ns t cs ce setup time 0 ns t ch ce hold time 10 ns t wp write pulse width 25 ns t als ale setup time 0 ns t alh ale hold time 10 ns t ds data setup time 20 ns t dh data hold time 10 ns t wc write cycle time 50 ns t wh we high hold time 15 ns t ww wp high to we low 100 ns t rr ready to re falling edge 20 ns t rp read pulse width 35 ns t rc read cycle time 50 ns t rea re access time (serial data access) 35 ns t cea ce access time (serial data access,id read) 45 ns t alea ale access time (id read) ns t ceh ce high time for last address in serial read cycle ns (2) t reaid re access time (id read) 35 ns t oh data output hold time 10 ns t rhz re high to output high impedance 30 ns t chz ce high to output high impedance 20 ns t reh re high hold time 15 ns t ir output-high-impedance-to- re falling edge 0 ns t rsto re access time (status read) 35 ns t csto ce access time (status read) 45 ns t rhw re high to we low 0 ns t whc we high to ce low 30 ns t whr we high to re low 30 ns t r memory cell array to starting address 25 p s t wb we high to busy 200 ns t ar2 ale low to re low (read cycle) 50 ns t rb re last clock rising edge to busy(in sequential read) 200 ns t cry ce high to ready(when interrupted by ce in read mode) 1+ tr( by / ry ) p s (1)(2) t rst device reset time (read/program/erase) 6/10/500 p s ac test conditions parameter condition input level 2.4 v, 0.4 v input pulse rise and fall time 3 ns input comparison level 1.5 v, 1.5 v output data comparison level 1.5 v, 1.5 v output load c l (100 pf) 1 ttl
TC58DVM72A1FTI0 2003-03-19 6/34 note: (1) ce high to ready time depends on the pull-up resistor tied to the by / ry pin. (refer to application note (9) toward the end of this document.) (2) sequential read is terminated when t ceh is greater than or equal to 100 ns. if the re to ce delay is less than 30 ns, by / ry signal stays ready. programming and erasing characteristics (ta =-40 to 85c, v cc 2.7 v to 3.6 v) symbol parameter min typ. max unit notes t prog programming time 200 1000 p s n number of programming cycles on same page 3 (1) t berase block erasing time 2 10 ms (1): refer to application note (12) toward the end of this document. : 0 to 30 ns o busy signal is not output. a ce re t ceh t 100 ns * 525 busy by / ry * : v ih or v il a 526 527
TC58DVM72A1FTI0 2003-03-19 7/34 timing diagrams latch timing diagram for command/address/data command input cycle timing diagram cle ale ce re we hold time t dh setup time t ds i/o1 to i/o8 : v ih or v il t cs t dh t ds t als t alh t wp t cls t ch t clh : v ih or v il ce cle we ale i/o1 to i/o8
TC58DVM72A1FTI0 2003-03-19 8/34 address input cycle timing diagram data input cycle timing diagram : v ih or v il we t wp t wp t wh t wp t als t wc t dh t ds d in 0 d in 1 t clh t ch ale cle ce i/o1 to i/o8 d in 527 t dh t ds t dh t ds t ch t cs t cs t dh t ds : v ih or v il t dh t ds t cls cle t als t wp t alh t wh t wp t wh t wp a0 to a7 t dh t ds a9 to a16 a17 to a23 t cs t wc t cs ce we ale i/o1 to i/o8 t ch
TC58DVM72A1FTI0 2003-03-19 9/34 serial read cycle timing diagram status read cycle timing diagram t whr we t dh t ds t cls t cls t cs t clh t ch t wp status output 70h * t whc t csto t ir t rsto t rhz t chz ce cle re by / ry i/o1 to i/o8 : v ih or v il t oh * 70h represents the hexadecimal number t reh t chz ce t rhz t rea t rc t rr t rhz t rea t rhz t rea re by / ry i/o1 to i/o8 t oh t oh t oh t rp t rp t rp t cea t ch
TC58DVM72A1FTI0 2003-03-19 10/34 read cycle (1) timing diagram read cycle (1) timing diagram: when interrupted by ce t cs t cls t clh t ch 00h a0 to a7 a9 to a16 a17toa23 d out n d out n 1 t dh t ds t wc t als t alh t alh t r t ar2 t rr t rc t rea t wb t chz we cle ce ale re by / ry column address n * d out n 2 t rhz : v ih or v il i/o1 to i/o8 t dh t ds t dh t ds t dh t ds t oh * read operation using 00h command n: 0 to 255 i/o1 to i/o8 t cs t cls t clh t ch 00h a0 to a7 a9 to a16 a17toa23 d out n d out n 1 t dh t ds t wc t als t alh t alh t r t ar2 t rr t rc t rea t wb we cle ce ale re by / ry : v ih or v il t dh t ds t dh t ds t dh t ds d out n 2 column address n * d out 527 * read operation using 00h command n: 0 to 255
TC58DVM72A1FTI0 2003-03-19 11/34 read cycle (2) timing diagram read cycle (3) timing diagram t cs t cls t clh t ch 50h a0 to a7 a9 to a16 a17toa23 d out t als t alh t alh t ar2 t rc t rea t wb we cle ce ale re by / ry column address n * d out d out t r t rr t dh t ds 512 m 512 m 1 i/o1 to i/o8 : v ih or v il t dh t ds 527 * read operation using 50h command n: 0 to15 t cs t cls t clh t ch 01h a0 to a7 a9 to a16 a17toa23 d out t als t alh t alh t ar2 t rc t rea t wb we cle ce ale re by / ry column address n * d out d out t r t rr t dh t ds 256 m 256 m 1 i/o1 to i/o8 : v ih or v il t dh t ds 527 * read operation using 01h command n: 0 to 255
TC58DVM72A1FTI0 2003-03-19 12/34 sequential read (1) timing diagram sequential read (2) timing diagram a0 to a7 a9 to a16 a17toa23 t r we cle ce ale re by / ry column address n n n 1 n 2 527 527 00h t r 0 1 2 page address m page m access page m 1 access : v ih or v il a0 to a7 a9 to a16 a17toa23 t r we cle ce ale re by / ry column address n 527 527 01h t r 0 1 2 page address m page m access page m 1 access : v ih or v il i/o1 to i/o8 256 n 256 n 1
TC58DVM72A1FTI0 2003-03-19 13/34 sequential read (3) timing diagram a0 to a7 a9 to a16 a17toa23 t r we cle ce ale re by / ry column address n 527 527 50h t r page address m page m access page m 1 access : v ih or v il i/o1 to i/o8 512 n 512 n 1 512 n 2 512 513
TC58DVM72A1FTI0 2003-03-19 14/34 auto-program operation timing diagram auto block erase timing diagram 60h a17toa23 we cle ce ale re by / ry : v ih or v il t cs t cls t clh t cls a9 to a16 t ds t dh t als : do not input data while data is being output. t alh d0h 70h t wb t berase busy status read command erase start command auto block erase setup command i/o1 to i/o8 status output 80h a9 to a16 a17toa23 t dh we cle ce ale re by / ry t prog : v ih or v il t cs t cls t clh t ch t cs t cls a0 to a7 d in 0 status output d in 527 d in 1 t wb 70h t ds t ds t dh t als t alh t alh t als 10h t ds t dh : do not input data while data is being output. i/o1 to i/o8 t ds t dh
TC58DVM72A1FTI0 2003-03-19 15/34 id read operation timing diagram : v ih or v il device code t alea we i/o1 to i/o8 t dh t ds t cls t cs t cls t ch 90h maker code ce cle re t cs t ch t alh t als t alh t cea 00 98h 73h t reaid address input ale t reaid
TC58DVM72A1FTI0 2003-03-19 16/34 pin functions the device is a serial access memory which utilizes time-sharing input of address information. the device pin-outs are configured as shown in figure 1. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command register from the i/o port on the rising edge of the we signal while cle is high. address latch enable: ale the ale signal is used to control loading of either address information or input data into the internal address/data register. address information is latched on the rising edge of we if ale is high. input data is latched if ale is low. chip enable: the device goes into a low-power standby mode when ce goes high during a read operation. the ce signal is ignored when device is in busy state ( by / ry l), such as during a program or erase operation, and will not enter standby mode even if the ce input goes high. the ce signal must stay low during the read mode busy st ate to ensure that memory array data is correctly transferred to the data register. write enable: the we signal is used to control the acquisition of data from the i/o port. read enable: the re signal controls serial data output. data is available t rea after the falling edge of re . the internal column address counter is also incremented (address address l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. write protect: the wp signal is used to protect the device from accidental programming or erasing. the internal voltage regulator is reset when wp is low. this signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. ready/busy: the by / ry output signal is used to indicate the operating condition of the device. the by / ry signal is in busy state ( by / ry l) during the program, erase and read operations and will return to ready state ( by / ry h) after completion of the operation. the output buffer for this signal is an open drain. ce we re wp by / ry nc nc nc nc nc gnd by / ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc nc nc 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 nc nc nc nc i/o8 i/o7 i/o6 i/o5 nc nc nc v cc vss nc nc nc i/o4 i/o3 i/o2 i/o1 nc nc nc nc figure 1 pinout
TC58DVM72A1FTI0 2003-03-19 17/34 schematic cell layout and address assignment the program operation works on page units while the erase operation works on block units. a page consists of 528 bytes in which 512 bytes are used for main memory storage and 16 bytes are for redundancy or for other uses. 1 page 528 bytes 1 block 528 bytes u 32 pages (16k 512) bytes capacity 528 bytes u 32 pages u 1024 blocks an address is read in via the i/o port over three consecutive clock cycles, as shown in table 1. table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 first cycle a7 a6 a5 a4 a3 a2 a1 a0 second cycle a16 a15 a14 a13 a12 a11 a10 a9 third cycle *l a23 a22 a21 a20 a19 a18 a17 a0~a7: column address a9~a23: page address a14~a23: block address a9~a13: nand address in block * : a8 is automatically set to low or high by a 00h command or a 01h command. * i/o8 must be set to low in the third cycle. 32 pages 1 block 16 512 i/o1 i/o8 8i/o 528 32768 pages 1024 blocks figure 2. schematic cell layout
TC58DVM72A1FTI0 2003-03-19 18/34 operation mode: logic and command tables the operation modes such as program, erase, read and reset are controlled by the ten different command operations shown in table 3. address input, command in put and data input/output are controlled by the cle, ale, ce , we , re and wp signals, as shown in table 2. table 2. logic table cle ale ce we re wp * 1 command input h l l h * address input l h l h * data input l l l h h serial data output l l l h * during programming (busy) * * * * * h during erasing (busy) * * * * * h program, erase inhibit * * * * * l standby * * h * * 0 v/vcc h: v ih , l: v il , * : v ih or v il * 1: refer to application note (10) toward the end of this document regarding the wp signal when program or erase inhibit ? table 3. command table (hex) first cycle second cycle acceptable while busy serial data input 80 read mode (1) 00 read mode (2) 01 read mode (3) 50 reset ff c auto program 10 auto block erase 60 d0 status read 70 c id read 90 table 4 shows the operation states for read mode. table 4. read mode operation states cle ale ce we re i/o1~i/o16 power output select l l l h l data output active output deselect l l l h h high impedance active standby l l h h * high impedance standby h: v ih , l: v il , * : v ih or v il 1 0 0 0 0 0 0 0 i/o8 7 6 5 4 3 2 i/o1 serial data input: 80h hex data bit assignment (example)
TC58DVM72A1FTI0 2003-03-19 19/34 device operation read mode (1) read mode (1) is set when a 00h command is issued to the command register. refer to figure 3 below for timing details and the block diagram. m=527 read mode (2) select page n the operation of the device after input of the 01h command is the same as that of read mode (1). if the start pointer is to be se t after column address 256, use read mode (2). by / ry we cle re m n start-address input busy 01h ce ale i/o cell array select page n m figure 4. read mode (2) operation 527 256 by / ry we cle re m n start-address input busy 00h ce ale i/o cell array m figure 3. read mode (1) operation m a data transfer operation from the cell array to the registe r starts on the rising edge of we in the third cycle (after the address information has been latched). the device will be in busy state during this transfer period. the ce signal must stay low after the third address input and during busy state. after the transfer period the device returns to ready state. serial data can be output synchronously with the re clock from the start pointer designated in the address input cycle.
TC58DVM72A1FTI0 2003-03-19 20/34 read mode (3) read mode (3) has the same timing as read modes (1) an d (2) but is used to access information in the extra 16-byte redundancy area of the page. the start pointer is ther efore set to a value between byte 512 and byte 527. m=527 , n=512 sequential read(1)(2)(3) this mode allows the sequential reading of pages without additional address input. sequential read modes (1) and (2) ou tput the contents of addresses 0~m as shown above, while sequential read mode (3) outputs the contents of the redundant addres s locations only. when the pointer reaches the last address, the device continues to output the data from this address ** on each re clock signal. m=527,n=512 a sequential read (1) (00h) 0 m a sequential read (2) (01h) a sequential read (3) (50h) n m by / ry 00h busy 01h busy busy address input t r data output data output t r t r n/2 by / ry we cle re busy 50h ce ale figure 5. read mode (3) operation 527 addresses bits a0~a3 are used to set the start pointer for the redundant memory cells, while a4~a7 are ignored. once a 50h command has been issued, the pointer moves to the redundant cell locations and only those 16 cells can be addressed, regardless of the value of the a4-to-a7 address. (an 00h command is necessary to move the pointer back to the 0-to-511 main memory cell location.) 512 a0~a3
TC58DVM72A1FTI0 2003-03-19 21/34 status read the device automatically implements the execution and verification of the program and erase operations. the status read function is used to monitor the ready/busy status of the device, determine the result (pass/fail) of a program or erase operation, and determine whether the device is in protect mode. the device status is output via the i/o port on the re clock after a 70h command input. the resulting information is outlined in table 5. table 5. status output table status output i/o1 pass/fail pass: 0 fail: 1 i/o2 not used 0 i/o3 not used 0 i/o4 not used 0 i/o5 not used 0 i/o6 not used 0 i/o7 ready/busy ready: 1 busy: 0 i/o8 write protect protect: 0 not protected: 1 the pass/fail status on i/o1 is only valid when the device is in the ready state. an application example with multiple devices is shown in figure 6. system design note: if the by / ry pin signals from multiple devices are wired together as shown in the diagram, the status read function can be used to determine the status of each individual device. device 1 cle 1 ce device 2 2 ce device 3 3 ce device n n ce device n 1 1 n ce ale we re i/o1 ~i/o8 by / ry we re status on device 1 70h 1 ce ale i/o 70h status on device n cle n ce figure 6. status read timing application example busy by / ry
TC58DVM72A1FTI0 2003-03-19 22/34 auto page program the device carries out an automatic page program oper ation when it receives a ?10h? program command after the address and data have been input. the sequence of command, address and data input is shown below. (refer to the detailed timing chart.) auto block erase the auto block erase operation starts on the rising edge of we after the erase start command ?d0h? which follows the erase setup command ?60h?. this two-cycle process for erase operations acts as an ertra layer of protection from aceidental erasure of data due to external noise. the device automatically executes the erase and verify operations. pass 80 10 data input 0 to 527 70 i/o address input data input command program command status read command fail by / ry by / ry automatically returns to ready after completion of the operation. figure 7. auto page program operation the data is transferred (programmed) from the register to the selected page on the rising edge of we following input of the ?10h? command. a fter programming, the programmed data is transferred back to the register to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. data input selected page reading & verification program pass i/o fail by / ry 60 d0 70 block address input: 2 cycles status read command busy erase start command
TC58DVM72A1FTI0 2003-03-19 23/34 reset the reset mode stops all operations. for example, in the case of a program or erase operation the internally generated voltage is discharged to 0 volts and the device enters wait state. the response to an ?ffh? reset command input during the various device operations is as follows: when a reset (ffh) command is input during programming when a reset (ffh) command is input during erasing when a reset (ffh) command is input during read operation when a status read command (70h) is input after a reset when two or more reset commands are input in succession figure 12. by / ry ff ff (3) (2) (1) the second command is invalid, but the third command is valid. ff ff ff internal v pp 80 10 ff 00 by / ry t rst (max 10 p s) figure 8. internal erase voltage d0 ff 00 by / ry t rst (max 500 p s) figure 9. 00 ff 00 by / ry t rst (max 6 p s) figure 10. figure 11. ff 70 by / ry i/o status: pass/fail o pass ready/busy o ready ff 70 by / ry i/o status: ready/busy o busy
TC58DVM72A1FTI0 2003-03-19 24/34 id read the device contains id codes which identify the device type and the manufacturer. the id codes can be read out under the following timing conditions: table 6. id codes read out by id read command 90h i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data maker code 1 0 0 1 1 0 0 0 98h device code 0 1 1 1 0 0 1 1 73h we cle re t cea ce ale i/o t alea t reaid id read command address 00 maker code figure 13. id read timing 90h 00 98h device code 73h for the specifications of the access times t reaid , t cea and t alea refer to the ac characteristics.
TC58DVM72A1FTI0 2003-03-19 25/34 application notes and comments (1) power-on/off sequence: the wp signal is useful for protecting against data corruption at power-on/off. the following timing sequence is necessary. the wp signal may be negated any time after the v cc reaches 2.5 v and ce signal is kept high in power up sequence. in order to operate this device stably, after v cc becomes 2.5 v, it recommends starting access after about 200 p s. (2) status after power-on the following sequence is necessary because some input signals may not be stable at power-on. (3) prohibition of unspecified commands the operation commands are listed in table 3. input of a command other than those specified in table 3 is prohibited. stored data may be corrupted if an unknown command is entered during the command cycle. (4) restriction of command while busy state during busy state, do not inpu t any command except 70h and ffh. (5) acceptable commands after serial input command ?80h? once the serial input command ?80h? has been input, do not input any command other than the program execution command ?10h? or the reset command ?ffh?. if a command other than ?10h? or ?ffh? is input, the program operation is not performed. ff reset power on figure 16. command other than ?10h? or ?ffh? 80 programming cannot be executed. for this operation the ?ffh? command is needed. 10 xx figure 15. power-on/off sequence don?t care don?t care ce , we , re cle, ale v il operation v il v ih wp 0 v v cc 2.7 v 2.5 v
TC58DVM72A1FTI0 2003-03-19 26/34 (6) addressing for program operation within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most significant bit) page of the block. random page address programming is prohibited. (7) status read during a read operation the device status can be read out by inputt ing the status read command ?70h? in read mode. once the device has been set to status read mode by a ?70h? command, the device will not return to read mode. therefore, a status read during a read operation is prohibited. however, when the read command ?00h? is input during [a], status mode is reset and the device returns to read mode. in this case, data output starts automa tically from address n and address input is unnecessary data in: data (1) page 0 data register page 2 page 1 page 15 page 31 (1) (2) (3) (16) (32) data (32) from the lsb page to msb page data in: data (1) page 0 data register page 2 page 1 page 15 page 31 (2) (16) (3) (1) (32) data (32) ex.) random page program (prohibition) figure 17. page programming within a block 00 address n command ce we by / ry re [a] status read command input status read status output figure 18. 70 00
TC58DVM72A1FTI0 2003-03-19 27/34 (8) pointer control for ?00h?, ?01h? and ?50h? the device has three read modes which set the destination of the pointer. table 8 shows the destination of the pointer, and figure 19 is a b lock diagram of their operations. table 8. pointer destination read mode command pointer (1) 00h 0~255 (2) 01h 256~511 (3) 50h 512~527 the pointer is set to region a by the ?00h? command, to region b by the ?01h? command, and to region c by the ?50h? command. (example) the ?00h? command must be input to set the pointer back to region a when the pointer is pointing to region c. to program region c only, set the start point to region c using the 50h command. 00h start point a area add 50h start point a area add start point c area add 50h add start point c area 00h start point c area add start point a area add 01h add start point b area start point a area add 50h add programming region c only figure 20. example of how to set the pointer 01h add programming region b and c 80h 80h 10h 10h start point b area start point c area din n/2-1 figure 19 pointer control pointer control (1) 00h (2) 01h (3) 50h m n/2 0 a c b n n-1
TC58DVM72A1FTI0 2003-03-19 28/34 (9) by / ry : termination for the ready/busy pin ( by / ry ) a pull-up resistor needs to be used for termination because the by / ry buffer consists of an open drain circuit. this data may vary from device to device. we recommend that you use this data as a reference when selecting a resistor value. v cc device v ss r by / ry c l t f ready v cc t r busy 1.5 p s 1.0 p s 0.5 p s 0 1 k : 4 k : 3 k : 2 k : 15 ns 10 ns 5 ns t f t r r t r t f ta 25c c l 30 pf figure 21. din
TC58DVM72A1FTI0 2003-03-19 29/34 (10) note regarding the wp signal the erase and program operations are automatically reset when wp goes low. the operations are enabled and disabled as follows: enable programming disable programming enable erasing disable erasing wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din
TC58DVM72A1FTI0 2003-03-19 30/34 (11) when four addre ss cycles are input although the device may read in a fourth address, it is ignored inside the chip. read operation program operation figure 23. cle address input 80h ignored ce we ale i/o data input figure 22. cle address input 00h, 01h, 50h ignored internal read operation starts when we goes high in the third cycle. ce we ale i/o by / ry
TC58DVM72A1FTI0 2003-03-19 31/34 (12) several programming cycles on th e same page (partial page program) a page can be divided into up to 3 segments. each segment can be programmed individually as follows: (13) note regarding the re signal re the internal column address counter is incremented synchronously with the re clock in read mode. therefore, once the device has been set to read mode by a ?00h?, ?01h? or ?50h? command, the internal column address counter is incremented by the re clock independently of the address input timing, if the re clock input pulses start before the address input, and the pointer reaches the last column address, an internal read operation (array to register) will occur and the device will enter busy state. (refer to figure 25.) hence the re clock input must start after the address input. data pattern 3 data pattern 1 all 1s figure 24. 1st programming 2nd programming 3rd programming resul t data pattern 1 data pattern 3 data pattern 2 all 1s data pattern 2 all 1s note: the input data for unprogrammed or previously programmed page segments must be ?1? all 1s figure 25. address input we i/o by / ry re 00h/01h/50h
TC58DVM72A1FTI0 2003-03-19 32/34 (14) invalid blocks (bad blocks) the device contains unusable blocks. therefore, at the ti me of use, please check whether a block is bad and do not use these bad blocks. at the time of shipment, all data bytes in a valid block are ffh. for bad block, all bytes are not in the ffh state. please don?t perform erase operation to bad block. check if the device has any bad blocks after installation into the system. figure 27 shows the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the performance of good blocks because it is isolated from the bit line by the select gate the number of valid blocks at the time of shipment is as follows: min typ. max unit valid (good) block number 1004 1024 block bad block test flow bad block bad block figure 26. pass read check start bad block * 1 block no. 1024 end read check : to verify the column address 517 bytes of the first page in the block with ffh yes fail figure 27 block no 1 no block no. block no. 1 * 1: no erase operation is allowed to detected bad blocks ?
TC58DVM72A1FTI0 2003-03-19 33/34 (15) failure phenomena for program and erase operations the device may fail during a program or erase operation. the following possible failure modes should be considered when implementing a highly reliable system. failure mode detection and countermeasure sequence block erase failure status read after erase o block replacement page programming failure status read after program o block replacement (1) block verify after program o retry single bit programming failure 1 o 0 (2) ecc x ecc: error correction code x block replacement program erase when an error occurs in an erase operation, prevent futu re accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) do not turn off the power before write/erase operation is complete. avoid using the device when the battery is low. power shoetage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. when an error happens in block a, try to reprogram the data into another block (block b) by loading from an external buffer. then, prevent further system accesses to block a (by creating a bad block table or by using an another appropriate scheme). block a block b error occurs buffer memory figure 28.
TC58DVM72A1FTI0 2003-03-19 34/34 package dimensions unit : mm weight: 0.53g (typ.)

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